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LH5268A
FEATURES * 8,192 x 8 bit organization * Access time: 100 ns (MAX.) * Power consumption: Operating: 220 mW (MAX.) 55 mW (MAX.) (tRC, tWC = 1 s) Standby: 220 W (MAX.) Data retention: 3.0 W (VCC = 3 V, TA = 25C) * Fully-static operation * Three-state outputs * Single +5 V power supply * TTL compatible I/O * Packages: 28-pin, 600-mil DIP 28-pin, 300-mil SK-DIP 28-pin, 450-mil SOP
CMOS 64K (8K x 8) Static RAM
DESCRIPTION
The LH5268A is a static RAM organized as 8,192 x 8 bits. It is fabricated using silicon-gate CMOS process technology.
PIN CONNECTIONS
28-PIN DIP 28-PIN SK-DIP 28-PIN SOP NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CE2 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4
5268A-1
TOP VIEW
Figure 1. Pin Connections for DIP, SK-DIP, and SOP Packages
1
LH5268A
CMOS 64K (8K x 8) Static RAM
ROW DECODERS
ROW ADDRESS BUFFER
A12 2 A8 25 A7 3 A6 4 A5 5 A4 6 A3 7
MEMORY ARRAY (128 x 512)
28 VCC 14 GND
I/O1 I/O2 I/O3 I/O4
11 12 13 15 I/O CIRCUITS DATA CONTROL COLUMN DECODER
I/O5 16 I/O6 17 I/O7 18 I/O8 19
COLUMN ADDRESS BUFFER
WE 27
OE 22 CE2 26 CE1 20 23 24 21 8 10 9 A11A9 A10 A2 A0 A1
5268A-2
Figure 2. LH5268A Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A12 CE1 - CE2 WE OE
Address inputs Chip Enable input Write Enable input Output Enable input
I/O1 - I/O8 VCC GND NC
Data inputs and outputs Power supply Ground No connection
2
CMOS 64K (8K x 8) Static RAM
LH5268A
TRUTH TABLE
CE1 CE2 WE OE MODE I/O1 - I/O8 SUPPLY CURRENT NOTE
H X L L L
NOTE: 1. X = H or L
X L H H H
X X L H H
X X X L H
Deselect Deselect Write Read Output disable
High-Z High-Z DIN DOUT High-Z
Standby (ISB) Standby (ISB) Operating (ICC) Operating (ICC) Operating (ICC)
1 1 1
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Supply voltage Input voltage Operating temperature Storage temperature
VCC VIN Topr Tstg
-0.3 to +7.0 -0.3 to V CC + 0.3 0 to +70 -65 to +150
V V C C
1 1,2
NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. VIN (MIN.) = -3.0 V for pulse width 50 ns.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Supply voltage Input voltage
VCC VIH VIL
4.5 2.2 -0.3
5.0
5.5 VCC + 0.3 0.8
V V V 1
NOTE: 1. VIN (MIN.) = -3.0 V for pulse width 50 ns.
DC CHARACTERISTICS (TA = 0 to +70C, VCC = 5 V 10%)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Input leakage current Output leakage current
ILI ILO
VIN = 0 to VCC CE 1 = VIH or CE2 = VIL or OE = VIH or WE = V IL VI/O = 0 V to VCC CE1 = VIL, VIN = VIL or VIH CE2 = VIH, II/O = 0 mA tCYCLE = 100 ns tCYCLE = 1.0 s
-1 -1
1 1 40
A A
Operating current
ICC
CE1 = 0.2 V, VIN = 0.2 V or VCC - 0.2 V CE2 = VCC - 0.2 V, II/O = 0 mA CE1 = VIH or CE2 = VIL CE2 0.2 V or CE1 VCC - 0.2 V IOL = 2.1 mA IOH = -1.0 mA
mA 10 3 40 0.4 2.4 mA A V V 1
ISB1 Standby current ISB VOL VOH
Output voltage
NOTE: 1. CE2 should be VCC - 0.2 V or 0.2 V when CE1 VCC - 0.2 V.
3
LH5268A
CMOS 64K (8K x 8) Static RAM
AC CHARACTERISTICS (1) READ CYCLE (TA = 0 to +70C, VCC = 5 V 10%)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Read cycle time Address access time Chip enable access time (CE1) (CE2)
tRC tAA tACE1 tACE2 tOE tOH (CE1) (CE2) tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ
100 100 100 100 40 10 10 10 5 0 0 0 30 30 20
ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1
Output enable access time Output hold time Chip enable to output in Low-Z
Output enable to output in Low-Z Chip enable to output in High-Z (CE1) (CE2)
Output disable to output in High-Z
NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
(2) WRITE CYCLE (TA = 0 to +70C, VCC = 5 V 10%)
PARAMETER SYMBOL MIN. MAX. UNIT NOTE
Write cycle time Chip enable to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Output active from end of write WE to output in High-Z OE to output in High-Z
tWC tCW tAW tAS tWP tWR tDW tDH tOW tWZ tOHZ
100 80 80 0 60 0 40 0 10 0 0 30 20
ns ns ns ns ns ns ns ns ns ns ns 1 1 1
NOTE: 1. Active output to high-impedance and high-impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER MODE NOTE
Input voltage amplitude Input rise/fall time Timing reference level Output load conditions
NOTE: 1. Includes scope and jig capacitance.
0.6 to 2.4 V 10 ns 1.5 V 1TTL + CL (100 pF) 1
4
CMOS 64K (8K x 8) Static RAM
LH5268A
CAPACITANCE 1 (TA = 25C, f = 1 MHz)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Input capacitance Input/output capacitance
CIN CI/O
VIN = 0 V VI/O = 0 V
7 10
pF pF
NOTE: 1. This parameter is sampled and not production tested.
DATA RETENTION CHARACTERISTICS (TA = 0 to +70C)
PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE
Data retention voltage Data retention current Chip disable to data retention Recovery time
VCCDR
CE2 0.2 V or CE1 VCCDR - 0.2 V VCCDR = 3 V, CE2 0.2 V or CE1 VCCDR - 0.2 V TA = 25C
2.0
5.5 1 20
V A A ns ns
1
ICCDR
1
tCDR tR
0 tRC
2
NOTES: 1. CE2 should be VCCDR - 0.2 V or 0.2 V when CE1 VCCDR - 0.2 V 2. t RC = Read cycle time
CE1 CONTROL (NOTE) VCC 4.5 V tCDR
DATA RETENTION MODE
tR
2.2 V VCCDR CE1 0V CE1 VCCDR - 0.2 V
CE2 CONTROL DATA RETENTION MODE VCC 4.5 V CE2 tCDR tR
VCCDR 0.8 V 0V CE2 0.2 V NOTE: To control the data retention mode at CE1, fix the input level of CE2 between VCCDR and VCCDR - 0.2 V or 0 V to 0.2 V during the data retention mode.
5268A-6
Figure 3. Low Voltage Data Retention
5
LH5268A
CMOS 64K (8K x 8) Static RAM
tRC
A0 - A12 tAA tACE1
CE1 tLZ1 tACE2 tHZ1
CE2 tLZ2 tOE tOLZ tHZ2
OE tOHZ tOH
DOUT NOTE: WE = 'HIGH.'
DATA VALID
5268A-3
Figure 4. Read Cycle
6
CMOS 64K (8K x 8) Static RAM
LH5268A
tWC
A0 - A12
OE tAW tCW (NOTE 2) CE1 tCW tWR tWR (NOTE 4)
CE2 tAS (NOTE 3) WE tOHZ tWP (NOTE 1) tWR
DOUT tDW tDH
DIN
DATA VALID
NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change.
5268A-4
Figure 5. Write Cycle 1
7
LH5268A
CMOS 64K (8K x 8) Static RAM
tWC A0 - A12 tAW tCW (NOTE 2) CE1 tCW tWR tWR (NOTE 4)
CE2 tAS (NOTE 3) WE (NOTE 6) DOUT tDW DIN tDH tWZ tOW (NOTE 7) tWP (NOTE 1) tWR
DATA VALID (NOTE 5)
NOTES: 1. The writing occurs during an overlapping period of CE1 = 'LOW,' CE2 = 'HIGH,' and WE = 'LOW' (tWP). 2. tCW is defined as the time from the last occuring transition, either CE1 LOW transition or CE2 HIGH transition, to the time when the writing is finished. 3. tAS is defined as the time from address change to writing start. 4. tWR is defined as the time from writing finish to address change. 5. When I/O pins are in the output state, input signals with the opposite logic level must not be applied. 6. If CE1 LOW transition or CE2 HIGH transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 7. If CE1 HIGH transition or CE2 LOW transition occurs at the same time or before WE HIGH transition, the outputs will remain high-impedance.
5268A-5
Figure 6. Write Cycle 2
8
CMOS 64K (8K x 8) Static RAM
LH5268A
PACKAGE DIAGRAMS
28DIP (DIP028-P-0600)
28 15
DETAIL
13.45 [0.530] 12.95 [0.510]
1 36.30 [1.429] 35.70 [1.406]
14
0 TO 15 0.30 [0.012] 0.20 [0.008] 15.24 [0.600] TYP.
4.50 [0.177] 4.00 [0.157] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 0.51 [0.020] MIN.
DIMENSIONS IN MM [INCHES]
28DIP-2
28-pin, 600-mil DIP
28DIP (DIP028-P-0300)
28 15 7.05 [0.278] 6.65 [0.262] 1 35.00 [1.378] 34.40 [1.354] 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.40 [0.134] 3.00 [0.118] 2.54 [0.100] TYP. 0.51 [0.02] MIN. 0.56 [0.022] 0.36 [0.014] MAXIMUM LIMIT MINIMUM LIMIT 14 0.35 [0.014] 0.15 [0.006] 7.62 [0.300] TYP.
DETAIL
0 TO 15
DIMENSIONS IN MM [INCHES]
28DIP-6
28-pin, 300-mil DIP
9
LH5268A
CMOS 64K (8K x 8) Static RAM
28SOP (SOP028-P-0450)
1.27 [0.050] TYP. 1.70 [0.067] 15 8.80 [0.346] 8.40 [0.331] 12.40 [0.488] 11.60 [0.457]
0.50 [0.020] 0.30 [0.012]
28
10.60 [0.417]
1 18.20 [0.717] 17.80 [0.701]
14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
28SOP
28-pin, 450-mil SOP
ORDERING INFORMATION
LH5268A Device Type X Package - ## Speed LL Power Low-Low-power standby 10 100 Access Time (ns) Blank 28 pin, 600-mil DIP (DIP028-P-0600) D 28-pin, 300-mil DIP (DIP028-P-0300) N 28-pin, 450-mil SOP (SOP028-P-0450) CMOS 64K (8K x 8) Static RAM Example: LH5268AD-10LL (CMOS 64K (8K x 8) Static RAM, Low-Low-power standby, 100 ns, 28-pin, 300-mil DIP))
5268A-7
10

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